Implementation of a 10 MS/s, 12-bit second-order noise-shaped continuous incremental analog-to-digital converter with segmented capacitor array using 90 nm CMOS process

The chip layout of the 10MS/s 12-Bit SAR ADC with split capacitor array and second-order noise-shaping in 90nm CMOS technology. The area of the circuit occupies 0.684 × 0.679 mm²

Sustainable Development Goals

Abstract/Objectives

This study focuses on designing a high-resolution, low-power Analog-to-Digital Converter (ADC) for CMOS Image Sensors (CIS). Traditional ADCs struggle to balance high speed, high resolution, and low power consumption. This design uses a noise-shaping architecture with second-order noise shaping to reduce in-band quantization noise, enhancing Signal-to-Noise and Distortion Ratio (SNDR). To address capacitance mismatch and maintain linearity, Mismatch Error Shaping (MES) technology is integrated. The circuit employs a Floating Inverter Amplifier (FIA) for efficient noise shaping, along with capacitance switching, bootstrapped switches, and StrongARM comparators. The goal is to achieve a 14-bit effective resolution at a 312.5 kHz bandwidth and 10 MHz sampling frequency, realized using TSMC's 90nm process. Simulation results reached 14.52 bits resolution, while actual measurements showed 13.46 bits, with total power consumption at 436 µW. The design achieved a Figure of Merit (FoM) of 171.4 dB.

Results/Contributions

This study aims to design and implement an Analog-to-Digital Converter (ADC) with high resolution and low power consumption for the back end of a CMOS Image Sensor (CIS). Traditional ADCs used in the back end array of CIS (such as single-slope ADCs) struggle to meet the triple constraints of high speed needed for high frame rates, high resolution required for high image quality, and low power consumption necessary for mobile devices. To address this, the design proposes a noise-shaping architecture, employing a second-order noise shaping method using integrator stacking to effectively suppress in-band quantization noise and significantly enhance Signal-to-Noise and Distortion Ratio (SNDR). Furthermore, to overcome the inherent capacitance mismatch issue of the C-DAC under process variations, this architecture integrates Mismatch Error Shaping (MES) technology to ensure that the linearity of the ADC is not affected by non-ideal factors such as harmonics. In terms of circuit implementation, to balance gain and power efficiency, the design employs a Floating Inverter Amplifier (FIA) as the core dynamic amplifier (DA) to achieve efficient and aggressive noise shaping. The core circuit also includes capacitance switching based on Vcm, bootstrapped switches, and StrongARM comparators. This design aims to achieve 14-bit effective resolution within a bandwidth of 312.5 kHz at a sampling frequency of 10 MHz. The circuits in this thesis are realized using TSMC's 90nm 1P9M CMOS process, with a core circuit area of 0.684 × 0.679 mm², operating voltage of 1.2V, and a sampling frequency of 10 MHz. Simulation results show an effective resolution of 14.52 bits at a bandwidth of 312.5 kHz; chip measurement results yield an effective resolution of 13.46 bits under the same bandwidth. The total power consumption of the chip under these conditions is measured at 436 µW, yielding a Figure of Merit (FoMs) of 171.4 dB when calculated.

Keywords

CMOS Image SensorAnalog to Digital ConverterNoise-ShapingSignal-to-Noise Distortion RatioMismatch Error ShapingFloating Inverter AmplifierSampling FrequencyEffective BitsPower ConsumptionFigure of Merit